Huawei just dropped a single Greek letter into the global chip conversation, and the industry hasn’t stopped talking about it since. On 25/05/2026, Huawei’s chip division head He Tingbo took the stage at the IEEE International Circuits and Systems Symposium and formally announced the τ (pronounced “tau”) Law. The claim is audacious: that the 60-year framework the entire semiconductor industry has lived by Moore’s Law needs to be replaced. In this article, we’ll unpack what the τ Law actually is, why it matters, and what it means for the future of computing.
About Moore’s Law
Before we can understand what τ Law is, we need to understand what it’s replacing.
In 1965, an Intel co-founder named Gordon Moore made an observation: the number of transistors on a chip doubled roughly every 2 years, and with each doubling, chips got faster and cheaper. The industry turned this observation into a roadmap. Generation after generation, chip makers raced to make transistors smaller, e.g. 90nm, 65nm, 45nm, 22nm, 7nm, 3nm, and the world got faster phones, laptops and data centres almost on schedule.
Think of it like a city road network. For decades, engineers solved traffic congestion by building more roads and making lanes narrower to fit more of them in. It worked brilliantly until you ran out of space.
That is roughly where the chip industry finds itself today. The “nanometre” labels on chips have become more marketing shorthand than physical measurement. Intel’s 10nm node has transistors that are actually around 18nm in size. Samsung’s 3nm and TSMC’s 3nm use entirely different architectures and neither reflects anything 3 nm in length. The number no longer describes anything you can measure with a ruler. It is just a name.
And making chips physically larger is not a straightforward workaround either. Manufacturing defects mean that the bigger a chip gets, the lower the probability it comes out working. Beyond a certain size, you end up throwing away too many chips to make the economics work.
Moore’s Law, in other words, has been running out of road.
About the τ Law
This is where Huawei’s proposal enters.
τ (tau) is a symbol from electrical engineering. In circuit theory, it represents the time constant. Specifically, the time it takes for a signal to stabilise after being triggered. It is calculated as resistance multiplied by capacitance, measured in seconds. In practical terms, it is the delay that lives inside every chip, in every wire, every connection, every gate, the tiny pauses between “send” and “receive” that accumulate invisibly across millions of operations per second.
Huawei’s τ Law proposes a shift in the fundamental measure of chip progress: from geometric shrinkage (i.e., how small can we make the transistor) to temporal shrinkage (i.e., how fast can we make the signal travel).
To use another analogy: imagine a relay race. Moore’s Law has been focused on shrinking the distance of the track. The τ Law says: stop worrying about the track length. Focus on how fast the baton gets passed.
This is not just a philosophical rebranding. It opens a genuinely different engineering path. This path doesn’t require access to the world’s most advanced chip fabrication equipment to pursue. For a company like Huawei, cut off from TSMC and the most advanced lithography machines by US export controls, this is significant.
The Engineering Idea Behind It: Logic Folding
The τ Law is not just a theory. It comes with a concrete engineering technique called Logic Folding.
In a traditional chip, all the logic gates (e.g., the tiny switches that do the actual computing) are laid out flat on a single silicon plane, like houses on a suburb street. The wires connecting them run horizontally through metal layers above. The longer those wires, the more delay they introduce into the critical path: the slowest chain of operations that determines how fast the chip can run.
Logic Folding takes that flat layout and folds it in half, then connecting them vertically. The long horizontal detours become short vertical hops. Signals travel less distance. Delays shrink. And a chip built on an older, less advanced fabrication process can suddenly punch above its weight class.
Think of it like a multi-storey car park versus a flat open lot. The flat lot can only hold so many cars per square metre of land. Stack it vertically, and you fit far more in the same footprint without needing a bigger block of land.
Huawei says this approach allows their upcoming Kirin 2026 chip (expected to launch in autumn 2026) to deliver performance equivalent to a 2nm process chip, despite being manufactured under significant process restrictions.
The Honest Challenges
The τ Law is not without its difficulties. Huawei acknowledges several in its own research paper.
The existing design tools, e.g., EDA software, are built for flat, single-layer chip design. They do not currently support the kind of cross-layer joint optimisation that Logic Folding requires. Process variation between different silicon layers is also significantly larger than within a single wafer, creating manufacturing consistency challenges. And each vertical connection between layers introduces its own small resistance and capacitance that has to be carefully managed. Otherwise, the folding gains are eaten up by the connection costs.
It is also fair to note that calling something a “law” is a big claim. Moore’s Law earned that name over more than a decade of observed industry data, validated repeatedly before being formally named in 1975. The τ Law, as of today, is closer to a methodology and a design philosophy. Whether it becomes an industry standard and whether chip makers beyond Huawei adopt it as a shared framework remains entirely open.
Summary
The τ Law represents an innovative shift in how we think about chip progress. Not smaller. Faster. Not shrinking the geometry of silicon. Shrinking the time it takes for information to move.
To bring it back to the road analogy one more time: Moore’s Law was about building more lanes. The τ Law is about removing traffic lights.
Whether or not the name sticks, this innovation represents that time delay is the true constraint to optimise for. The industry will be grappling with it for the next decade. And the Kirin 2026, arriving later this year, will be the first real-world test of whether the theory holds. The first answer is coming soon!